High-Level Power Analysis and Optimization

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Product Description

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

High-Level Power Analysis and Optimization Review

A very good overview of techniques for power estimation and minimization above the logic level. Unlike a large number of Kluwer books which are re-published PhD theses, this one actually presents a survey of various techniques. I found the chapters on register-transfer level power estimation and power management especially useful.Overall, this book is a great source of information if you are looking for an overview of different techniques to model or minimize power consumption in RTL designs. Help other customers find the most helpful reviews� Was this review helpful to you?�Yes No Report abuse | PermalinkComment�Comment

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