Networks on Chip

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Product Description

As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

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Networks on Chip Review

Modern chip-based systems, whether ASICs or FPGA, have grown so large that monolithic designs are often infeasible. Instead, processors, DSPs, IOs, and other functions are implemented as individual units, then connected with some common communication fabric. In fact, single-chip designs now have the same kinds of communication needs met by PC backplanes and by the different kinds of interconnect in supercomputers. This book summarizes the state of the art in NoC research as of the year it was written, 2003.

Issues exist at every level, from clock distribution up to programming models and operating systems. Various chapters in this book address all of those concerns. The editors invited a range of experts to contribute chapters in their areas of expertise, in three major areas: methodology, hardware, and software. Each section offers significant food for thought, starting with the first.

That introduction, written by the editors, proposes two features are requirements for scalable systems: arbitrary composability, and the linear effort property. The first, being able to attach any component to any other, certainly echoes the ideas of backplanes and LANs. Still, backplane systems have "top hats" and other special connectors along with the standard interconnection. Likewise I think there's room for more than the one communication path, especially when the chip fabrics offer nearly infinite possibilities for custom communication. The second requirement, that composition require only linear effort instead of polynomial or worse, sounds audacious by the standards of today's designs. If anything, I'd hope for sublinear effort, either by replication of composite sub-assemblies or through use of repetitive arrays of processing elements with regular communication paths.

Hardware specifics interest me only as background issues. Instead, the software systems mean more to me, including the real time executives and communication APIs that create higher level couplings between on-chip subsystems. It surprised me, but shouldn't have, that everything from LAN APIs to MPI and supercomputing technologies are on the table. As single chips grow into large scale systems, large scale computing technologies make increasing sense.

Jantsch and Tenhunen have assembled a good survey of NoC concerns, with an extensive bibliography in each chapter. Presentation is generally at a high conceptual level, well suited to the book's purpose but possibly disappointing to practitioners with immediate problems to solve. I recommend it to anyone working in the design of complex on-chip systems and their development tools.

-- wiredweird

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